diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index f492b04..645b4ce 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -256,6 +256,20 @@
 config SYS_FSL_IFC_BE
 	bool
 
+config SYS_FSL_IFC_BANK_COUNT
+	int "Maximum banks of Integrated flash controller"
+	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
+		ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
+		ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
+		ARCH_T2080 || ARCH_C29X || ARCH_P1010 || ARCH_BSC9131 || \
+		ARCH_BSC9132
+	default 3 if ARCH_BSC9131 || ARCH_BSC9132
+	default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
+			ARCH_B4420 || ARCH_P1010
+	default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
+			ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || \
+			ARCH_T1024 || ARCH_T2080 || ARCH_C29X
+
 config FSL_QIXIS
 	bool "Enable QIXIS support"
 	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index a83eb7e..64fea9a 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -102,10 +102,6 @@
 config SYS_HAS_SERDES
 	bool
 
-config SYS_FSL_IFC_BANK_COUNT
-	int "Maximum banks of Integrated flash controller"
-	default 8
-
 config SYS_FSL_ERRATUM_A008407
 	bool
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 9656c52..dcb1ca5 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -525,13 +525,6 @@
 	  Offset for CCI400 base
 	  CCI400 base addr = CCSRBAR + CCI400_OFFSET
 
-config SYS_FSL_IFC_BANK_COUNT
-	int "Maximum banks of Integrated flash controller"
-	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
-	default 4 if ARCH_LS1043A
-	default 4 if ARCH_LS1046A
-	default 8 if ARCH_LS2080A || ARCH_LS1088A
-
 config SYS_FSL_HAS_CCI400
 	bool
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index d731ac3..03e86d8 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -16,9 +16,6 @@
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
-#elif defined(CONFIG_ARCH_P1010)
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
-
 #elif defined(CONFIG_ARCH_P1021)
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
@@ -85,11 +82,6 @@
 #define CFG_SYS_FM_MURAM_SIZE	0x28000
 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
-#elif defined(CONFIG_ARCH_BSC9131)
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
-
-#elif defined(CONFIG_ARCH_BSC9132)
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 
 #elif defined(CONFIG_ARCH_T4240)
 #ifdef CONFIG_ARCH_T4240
@@ -110,7 +102,6 @@
 #define CFG_SYS_FSL_SRDS_4
 #define CFG_SYS_NUM_FMAN		2
 #define CFG_SYS_PME_CLK		0
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FM1_CLK		3
 #define CFG_SYS_FM2_CLK		3
 #define CFG_SYS_FM_MURAM_SIZE	0x60000
@@ -123,7 +114,6 @@
 #define CONFIG_SYS_FSL_SRDS_2
 #define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_FM1_CLK		0
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CFG_SYS_FM_MURAM_SIZE	0x60000
 
 #ifdef CONFIG_ARCH_B4860
@@ -146,7 +136,6 @@
 #define CFG_SYS_NUM_FM1_DTSEC	5
 #define CFG_PME_PLAT_CLK_DIV		2
 #define CFG_SYS_PME_CLK		CFG_PME_PLAT_CLK_DIV
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_FM_PLAT_CLK_DIV	1
 #define CFG_SYS_FM1_CLK		CFG_FM_PLAT_CLK_DIV
 #define CFG_SYS_FM_MURAM_SIZE	0x30000
@@ -161,7 +150,6 @@
 #define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_NUM_FM1_DTSEC	4
 #define CFG_SYS_NUM_FM1_10GEC	1
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FM1_CLK		0
 #define CFG_QBMAN_CLK_DIV		1
 #define CFG_SYS_FM_MURAM_SIZE	0x30000
@@ -185,13 +173,11 @@
 #define CFG_PME_PLAT_CLK_DIV		1
 #define CFG_SYS_PME_CLK		CFG_PME_PLAT_CLK_DIV
 #define CFG_SYS_FM1_CLK		0
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FM_MURAM_SIZE	0x28000
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 
 
 #elif defined(CONFIG_ARCH_C29X)
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FSL_SEC_IDX_OFFSET	0x20000
 
 #endif